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Scholars Journal of Engineering and Technology | Volume-11 | Issue-10
FPGA Implementation of Efficient CDF-9/7 Discrete Wavelet Transform
Roopa K. C, Chetan S
Published: Oct. 3, 2023 | 414 587
DOI: 10.36347/sjet.2023.v11i10.001
Pages: 225-238
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Abstract
Architecture CDF-5/3 DWT is utilized to derive CDF-9/7 DWT. Because of the prevalence of fractional parts in the generic CDF 9/7 architecture and the occurrence of truncation errors, the design is difficult to execute. Since the CDF-5/3 DWT filter allows for the employment of merely a shifter, attempted to design the CDF-9/7 DWT filter in this manner so that the truncation error is as little as possible, if not eliminated.