DOI: 10.36347/sjet.2023.v11i11.002

Pages: 287-292

This research paper presents design & simulation of a high performance five stage pipelined 8 bit or 16-bit Microprocessor without Interlocked Pipeline Stages (MIPS), which is a Reduced Instruction Set Computing (RISC) architecture based processor. The purpose of RISC microprocessor is to execute a minuscule batch of instructions, with the intention of proliferating the celerity of the processor. This processor was designed with 5 phases of pipeline in particular Instruction Fetch (IF), Instruction Decode & Register Fetch (ID), Execution & Address Calculation (EX), Memory Access (MEM) and Write Back (WB) modules. The designing process was done using a myriad of modules which are the ALU, Control Unit, Program Counter, MUX, Instruction Memory, Data Memory, CPU, Register File, and Sign Extension. The Proposed design is developed by Verilog HDL and Simulated by Modelsim 6.4 c and Synthesized by Xilinx tool and proposed system implemented in FPGA Spartan 3 XC3S 200 TQ-144.