DOI: DOI: https://doi.org/10.36347/sjet.2025.v13i03.003

Pages: 176-186

Although deep learning has progressed the field of artificial intelligence (AI), the traditional digital computing architectures are still limited by the von Neumann bottleneck. The continuous fetching and loading of the information results in high latency and excessive energy consumption, making AI optimization difficult. To address these issues, this paper proposes a solution that utilizes a hybrid analog-digital neural network processor by incorporating analog in-memory computing (AIMC) with digital computation for efficient AI model training and inference. The use of resistive random-access memory (RRAM) and electrochemical random-access memory (ECRAM) is harnessed for training since both allow data to be used as electrically programmable non-volatile memory, enabling data to be stored and processed without the need for constant transfers, thus increasing speed and reducing power use. For AI inference, phase-change memory (PCM) is used to perform the computations with the use of analog synaptic cells, which provides increase energy and processing efficiency. The new architecture is able to achieve greater computational efficiency along with low energy spending and increase processing speed by integrating the parallel processing capabilities of the analog memory and precision reading and writing of the digital processor, improving AI inference lag times. The results take AI workloads to be much more scalable and efficient outlined why the new architecture leads the standard digital processors with speed tests. This research outlines the prospects hybrid analog-digital processors which can change how next-gen AI systems with the ported compute like never before with limitless development.