DOI: https://doi.org/10.36347/sjet.2025.v13i09.001

Pages: 708-717

The rapid evolution of embedded systems has amplified the demand for intelligent, energy-efficient, and scalable computing platforms capable of handling data-intensive workloads in domains such as IoT, autonomous systems, and healthcare. Traditional VLSI design approaches, while effective at circuit-level optimization, struggle to meet the requirements of modern deep learning applications due to energy, latency, and scalability constraints. This paper presents a synergistic co-design framework that integrates hardware-aware deep learning models with VLSI-based accelerators to achieve significant gains in throughput, energy efficiency, and latency reduction. By leveraging techniques such as pruning, quantization, parallelism, and pipelining, the proposed framework aligns algorithmic efficiency with hardware constraints, ensuring real-world feasibility in resource-constrained environments. Experimental evaluations on CIFAR-10, ImageNet, and IoT workloads demonstrate up to 3.5× performance improvements with minimal accuracy loss. FPGA-based prototypes further validate the framework’s adaptability for edge intelligence, paving the way for next-generation embedded platforms optimized for power, scalability, and application-specific intelligence.