DOI: 10.36347/sjet

Pages: 769-773

Hardware development of cryptographic algorithms is subject to various attacks. It has been previously demonstrated that scan chains introduce for hardware testability open a back door to potential attacks. Scan based testing is one of the mainly used and powerful test technique since it provides full observability and controllability of the internal nodes of the IC. It has been previously demonstrated that scan chains introduced for hardware testability open a back door to possible attacks. Here, we propose a scan-protection scheme that provides testing facilities both at production time and over the course of the circuit’s life. Here the underlying principles to scan-in both input vectors and expected responses and to compare expected and actual responses inside the circuit. Compared to regular scan tests, this technique has no impact on the quality of the test or the model-based fault diagnosis. It entails negligible area overhead and avoids the use of an authentication test mechanism