DOI: 10.36347/sjet

Pages: 672-678

This paper describes PIC12C5xx a pipelined processor design and implementation on Xilinx FPAG Chip, which named KAUPIC12. This project is conducted for the Computer Organization Course (EE361) at King Abdulaziz University. The project design has three main stages: one for the assembler design using the Java Eclipse software, the second stage is the single cycle design and the last stage is the pipelined design. The project course was a complete help for the students to understand the operations of pipelined processors and to excel in using the Basys 2 FPGA Board.