DOI: 10.36347/sjet

Pages: 228-233

In our today’s world the communication without the fault can be required. In signal processing there are many filters can be achieved for the communications such as the digital filters, FIR filters and the parallel filters. For the kind of error fault detection the parallel filters must be suited for the high level applications. The parallel filters with fault tolerance have been proposed here to detect the multiple errors present in the communication channels. The error recovery could be done by using the hamming code and the extended hamming codes. The hamming code can be proposed for the single bit error tolerance and the extended hamming code can be achieved for the multiple bit error detection. The fault tolerance architecture having this error correction method can be very less power, area and the delay consumption. The parallel filter architecture with error correction must be suitable for the high stable communication with high reliability. The most required system for the applications may be considered for the single event test in the parallel architecture. The high secure communication with the multiple bit errors can also to be recognized from the channel length of the input signal. This architecture can be less latency with its high number of the latches. The on-data path pipelines for this process can be varied from the structure for the event based signals. These hamming codes with the error detection and correction for the single bit and the multiple bits can be achieved. The process variation and its implementation can be achieved by using the Xilinx ISE software. The power analysis can be done through the X power analyzer.